Continuous output current, I. When the latch enable input. A buffered output-enable OE input can be used to place the eight outputs in either a normal logic state high or low logic levels or the high-impedance state. The package thermal impedance is calculated in accordance with JESD The device is fully specified for partial power down applications using I OFF. To Seven Other Channels. No purposely added lead.
Lead Temperature 10 sec.
High or low state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
Refer to the TI application report. OE does not affect the internal operations of the latches.
Time D to Q. This is a individually operated, non profit site. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.
In the high- impedance state, the outputs neither load nor drive the bus lines significantly. Input transition rise or fall rate. Time LE to Q. These devices feature inputs and outputs on opposite sides of the. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
Input Rise and Fall Time note 2. While the latch-enable LE input is high, the Q outputs follow the data D inputs. Output clamp current, I.
Low voltage and high-speed operation is suitable at the battery drive product note type personal. Inputs can be driven from either 3. Please consult the sales office for the above package availability. Refer to Test Circuit.
74LVCA Datasheet pdf — Octal Transparent D-Type Latch with 3-State Outputs — Diodes
When a high logic level is applied to the output control input, all. Pulse duration, LE high. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is ideal for 1.
High impedance Q 0: Old data can be retained or new data can be но while the outputs are in the high-impedance state. Old data can be retained or new data can be entered while. Level of Q before the indicated steady input conditions were established. Products conform to specifications per the terms of Texas Instruments. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.
74LVC573A Datasheet (PDF) — STMicroelectronics
No purposely added lead. Supply Voltage note 1. Production processing does not necessarily include. This publication supersedes and replaces all information. Setup Time D to LE, 1.